As semiconductor integrated circuit devices have become more highly integrated to provide greater processing and/or memory capacity, chip sizes and deposition thickness have also increased. Accordingly, semiconductor wafer diameters have increased to provide increased numbers of the larger integrated circuit devices thereon. In other words, larger diameter semiconductor wafers can be used to fabricate larger numbers of integrated circuit devices.
The total thickness of layers deposited on semiconductor wafers may also increase because the more highly integrated devices may include a greater number of layers. Accordingly, more highly integrated devices may include a greater number of deposition, heat treatment, photolithography, and etching steps during the fabrication thereof, and the resulting stresses may cause the wafer to warp. In particular, depositions and thermal treatments at high temperatures of hundreds of degrees Celsius may stress the semiconductor wafer and cause warping.
For example, wafer warping has been observed during the fabrication of 64 M dynamic random access memory (DRAM) devices, and wafer warping is likely to increase with higher capacity memory devices and with the use of larger diameter wafers. For example, when forming a polysilicon layer to provide gate electrodes for a DRAM, polysilicon layers may be formed on both the device side of the wafer and the backside of the wafer. Only the polysilicon layer on the device side of the wafer, however, is typically patterned so that differences in the stresses due to thermal expansion caused by the patterned and unpatterned polysilicon layers may cause wafer warping.
A technique for reducing warping is discussed in Japanese Patent Application No. 4-302432 which has been laid open. In the 4-302432 application, grooves are formed in the polysilicon layer on the backside of the wafer. Formation of these grooves, however, may make it difficult to hold the device side of the wafer even so that it is difficult to ensure focus margins during subsequent photolithography exposure steps. In other words, the grooves in the polysilicon layer on the backside of the wafer may make it difficult to support the wafer during photolithography exposure steps so that the device side of the wafer is maintained within a common focal plane. Furthermore, while this technique may reduce concave wafer warping, this technique may not address convex wafer warping.